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Conceptualize a Design Flow for 2-D Bitstream Relocation

date
17.04.2018 
time
01:00 PM - 02:00 PM 
speaker
Najdet Charaf 
affiliation
Institut für Technische Informatik, Professur Prozessordesign 
language
en 
main topic
Computer Science: Artificial Intelligence, Bioinformatics, Technical Informatics and HPC, Image Processing, Machine Learning
abstract

Runtime partial reconfiguration provides a high flexibility and time share capabilities on FPGAs. However, designs with several reconfigurable partitions (RPs) and several reconfigurable modules (RMs) generate a lot of partial bitstreams (PBs) for all possible RP/RM pairs. In addition, the time needed to generate all PBs increases with the number of RPs and RMs. For this purpose, bitstream relocation is an approach that provides a less storage usage and reduces the time needed for generating all possible PBs. This diploma thesis presents an automated floorplanning approach and a fully automated design flow for 1-D and 2-D bitstream relocation. The algorithm was implemented for Xilinx Vivado Design Suite and works on any Xilinx Series 7 devices. Diese Veranstaltung wird unterstützt von Professur Prozessordesign.

 

Last update: 17.04.2018 07:49.

venue 

TUD Georg-Schumann-Bau (Georg-Schumann-Str. 7A, 2. OG Raum 204) 
Münchner Platz 3
01187 Dresden
homepage
https://navigator.tu-dresden.de/etplan/sch/00 

organizer 

TUD Informatik
Nöthnitzer Straße 46
01069 Dresden
telefon
+49 (0) 351 463-38465 
fax
+49 (0) 351 463-38221 
homepage
http://www.inf.tu-dresden.de 
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