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Implementation of the Platform Integration for the Backend of the Neural Network Inference Engine Generator FINN Emphasizing the Efficient Execution of Multi-Layer Offload Schedules

date
18.06.2018 
time
10:00 AM - 11:00 AM 
speaker
Björn Gottschall 
affiliation
Institut für Technische Informatik, Professur Prozessordesign 
language
en 
main topic
Computer Science: Artificial Intelligence, Bioinformatics, Technical Informatics and HPC, Image Processing, Machine Learning
abstract

Artificial intelligence and machine learning has become an important research domain and is already found in many applications of everyday life, like speech recognition and synthesis for personal assistants, autonomous driving, object and face detection, translations and many more. Neural networks are playing a special role in this context, as they can be designed and trained to solve formerly intractable problems, especially in image classification and object detection.

This work proposes a platform integration for neural network inference, which is highly optimized and offers a uniform code base, that can easily be adapted to new network types and hardware platforms. The special focus are Multilayer Offload networks, which are designed to run with limited hardware resources and pose unprecedented demands to an interface driving neural networks. Highly quantized or even binarized neural networks are the key requirement to enable reprogrammable hardware to compete in inference processes with ASCIs or GPUs. DoReFaNet and Tinier-YOLO, two reduced precision Multilayer Offload networks, are currently covered by the new platform integration and potentially every convolutional network from FINN, a generator for neural network inference accelerators. Special layer implementations, which are not covered by hardware, and memory reorganization on bit level offered many optimization potentials compared to old specialized interface implementations. Together with batch processing on the interface side and support for multi-threading, the new unified platform integration increased performance drastically for each covered network. Diese Veranstaltung wird unterstützt von Professur Prozessordesign.

 

Last update: 11.06.2018 08:06.

venue 

TUD Barkhausen-Bau (BAR III81/82 (Meetingraum 3. Etage)) 
Helmholtzstraße 18
01087 Dresden
homepage
https://navigator.tu-dresden.de/etplan/bar/00 

organizer 

TUD Informatik
Nöthnitzer Straße 46
01069 Dresden
telefon
+49 (0) 351 463-38465 
fax
+49 (0) 351 463-38221 
homepage
http://www.inf.tu-dresden.de 
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