Probabilistic Model Checking for Fault-Tolerance Techniques (Statusvortrag)

Datum

10.10.2017

Zeit

10:10 - 11:10

Sprecher

Dipl.-Inf. Linda Leuschner

Sprache

en

Hauptthema

Informatik

Andere Themen

Informatik

Beschreibung

Today's computer systems suffer from increasing bit-flips rates, triggered by transistors becoming smaller and smaller and more prone to transient errors. Thus, fault-tolerance is of increasing interest. Well-known and newly developed fault-tolerance techniques cover a large range of computer architectures, fault models, and overhead tradeoffs. Evaluation of these techniques is typically done by running fault-injections or simulations. Due to the complexity of today's hardware and software, this cannot guarantee to provide reliable results. Furthermore, many fault-tolerance mechanisms comprise configuration parameters, e.g., the number of data copies to be maintained or the percentage of redundancy to be added. Thus, finding a well-suited technique is also a configuration problem. Due to the large span of possible configurations it is often impossible to find an optimal configuration using simulation techniques. Betreuerin: Prof. Dr. Christel Baier Fachreferent: Prof. Dr. Christof Fetzer In this talk we illustrate the applicability of probabilistic model checking (PMC) as a quantitative evaluation method for fault-tolerant systems, that also supports finding good parameter settings. We present two concrete systems that are evaluated and configured using PMC. The first case study is a set of processes communicating via an inter-process communication protocol as developed for the Fiasco.OC microkernel. The communication channels of these processes are affected by and shall be protected against bit-flips. Second, we look at applications that are protected against bit-flips by transaction- and redo-based resilience techniques. We report on pitfalls that arose during evaluation, concerning the well-known state-space explosion problem as well as accuracy when handling small error probabilities. We show how these pitfalls can be overcome in the context of fault-tolerance evaluation and report on first evaluation and configuration results.

Letztmalig verändert: 10.10.2017, 09:36:47