FPGAs, Parallelism, Multi-Core

Date

Jan 25, 2011

Time

1:00 PM - 2:00 PM

Speaker

Jens Teubner

Affiliation

ETH Zürich

Language

en

Main Topic

Informatik

Other Topics

Informatik

Host

Wolfgang Lehner

Description

While the "multi-core era" still sees a steep increase in the available degrees of hardware parallelism, it still remains a hard challenge to use this parallelism efficiently and for real-world tasks. Field-programmable gate arrays (FPGAs) are a particularly extreme case. With relatively low clock speeds, performance can only be gained by massively parallelizing any given task. This, in turn, may require radically new approaches to problems that seem well-understood in software. One such case is the "frequent item" problem, a classical data mining task. In the talk I will demonstrate a solution that I developed in the context of the "Avalanche" project at ETH Zurich. It is radically different to existing approaches and reaches a more than four-fold throughput advantage on standard FPGA hardware. Such results on FPGA hardware are all the more interesting, when their design techniques can also be mapped to other hardware environments, such as modern multi-core systems with very large core counts. I will exemplify this in the talk with a task from the stream processing context. With "handshake join" I developed a stream join algorithm that achieves unprecedented throughput on commodity hardware. This is made possible by pipelining the operation and parallelizing it over arbitrarily many CPU cores (I tested on an AMD system with 48 cores). The work I present has been carried out in the SNF-funded project "Avalanche" (http://www.systems.ethz.ch/research/projects/avalanche).

Last modified: Jan 25, 2011, 11:44:45 AM